1. Field of the Invention
The present invention relates to an insulated gate semiconductor device such as an insulated gate bipolar transistor (hereinafter abbreviated as "IGBT") and a method of manufacturing the same.
2. Description of the Prior Art
An insulated gate bipolar transistor is a semiconductor device which has a structure in which p-type semiconductor regions and n-type semiconductor regions are joined so that at least four semiconductor regions of alternate conductivity type are disposed in series. The two outer semiconductor regions, at least, are electrically connected to a positive and a negative main electrodes, respectively. To one of the two inner semiconductor regions, a gate electrode for applying an electric field is connected through an insulating thin film. In this type of semiconductor device, a current which flows between the two main electrodes changes in accordance with a voltage which is applied to the gate electrode. An IGBT, an EST (Emitter Switched Thyristor), a MCT (MOS Controlled Thyristor) and the like fall within this category of semiconductor device.
&lt;Structure of Conventional Device&gt;
FIG. 20 is a cross sectional view showing the structure of a conventional N-channel type IGBT. In general, an IGBT is comprised of a number of IGBT elements (hereinafter "unit cells") which are connected parallel to each other. FIG. 20 shows a cross section of one unit cell. In this IGBT, an n-type semiconductor layer 11 is formed on a p-type semiconductor layer 1 which includes a p-type semiconductor substrate, whereby a semiconductor substrate body 12 is formed. Locally in the top major surface of the n-type semiconductor layer 11, i.e., in the top major surface of the semiconductor substrate body 12, a p-type base region 4 is formed by selective diffusion of p-type impurities. Also locally in the top major surface of the semiconductor substrate body 12, an n-type emitter region 5 is formed by selective diffusion of n-type impurities. On top surface of the p-type base region 4 between the top surface of the n-type semiconductor layer 11 and the top major surface of the n-type emitter region 5, a gate insulation film 7 is disposed. On the gate insulation film 7, a gate electrode 8 which is made of polycrystalline silicon (hereinafter simply as "polysilicon") is formed.
An emitter electrode 9 made of aluminum is disposed in electrical connection to both the p-type base region 4 and the n-type emitter region 5. The gate electrode 8 and the emitter electrode 9 are insulated from each other. The gate electrodes 8 of the respective unit cells are electrically connected with each other and the emitter electrodes 9 of the respective unit cells are also electrically connected with each other. A collector electrode 10 which is made of metal such as aluminum is electrically connected to the bottom major surface of the p-type semiconductor layer 1. The collector electrodes 10 of the respective unit cells are contiguous with each other.
The n-type semiconductor layer 11 includes a buffer layer 2 which is heavily doped n-type where it abuts the p-type semiconductor layer 1. In the class of IGBT having withstand voltage of 600 V, within the n-type semiconductor layer 11, the n-type semiconductor layer 3 excluding the buffer layer 2 has an impurity concentration of about 10.sup.14 cm.sup.-3 (In general, the withstand voltage becomes higher in proportion to decrease of the impurity concentration. The following description will be made for the IGBT having a withstand voltage class of 600 V.) In the buffer layer 2, on the other hand, the concentration of n-type impurities is about 10.sup.17 cm.sup.-3.
&lt;Operations of Conventional Device&gt;
Now, the operation of the conventional device will be explained. First, a predetermined collector voltage V.sub.CE is applied between the emitter electrode 9 and the collector electrode 10. If in addition to this, a gate voltage V.sub.GE exceeding a threshold value which the device inherently has is applied between the emitter electrode 9 and the gate electrode 8, the p-type base region 4 is inverted into the n-type at a channel region 6 which is located in the vicinity of the gate electrode 8, thereby creating an n-type channel at the channel region 6. Through this channel, carriers, in this case electrons, are introduced from the emitter electrode 9 into the n-type semiconductor layer 3. Due to the introduced electrons, a forward bias is applied between the p-type semiconductor layer 1 and the n-type semiconductor layer 11, causing injection of carriers, i.e., holes in this case, from the p-type semiconductor layer 1. As a result, the resistance of the p-type semiconductor layer 1 drops largely so that a collector current I.sub.c flowing from the collector electrode 10 to the emitter electrode 9 drastically increases. In other words, the device turns conductive (i.e., turns on). A resistance against the collector current I.sub.c at such an occasion is called an ON-resistance. The ON-resistance is in most cases expressed as the collector voltage V.sub.CE when the collector current I.sub.c is equal to a normal rated current value (i.e., saturation collector voltage V.sub.CE (sat)). The normal rated current of the conventional IGBT is typically around 50 to 150 A/cm.sup.2. Thus, in the IGBT, the resistance of the n-type semiconductor layer 11 is reduced by means of injection of holes from the p-type semiconductor layer 1.
FIG. 21 is a graph showing output characteristics of the device in response to various gate voltages V.sub.GE. When the collector voltage V.sub.CE is increased while the gate voltage V.sub.GE of a certain value is applied, the flow rate of electrons flowing in the channel is suppressed by a certain amount which corresponds to the gate voltage V.sub.GE. For this reason, the collector current I.sub.c flowing in the device saturates at a constant value which corresponds to the gate voltage V.sub.GE, that is, at a saturation collector current I.sub.c (sat) (horizontal straight portions of the curves in FIG. 21).
The buffer layer 2 controls injection of holes from the p-type semiconductor layer 1. In the buffer layer 2, due to a high concentration of the n-type impurities, holes from the p-type semiconductor layer 1 easily combine with electrons which exist in the buffer layer 2. Hence, provision of the buffer layer 2 lowers the saturation collector current I.sub.c (sat) while enhances the ON-resistance. By adjusting the thickness and the impurity concentration of the buffer layer 2, the saturation collector current I.sub.c (sat) and the ON-resistance can be adjusted.
If the gate voltage V.sub.GE is suppressed under the threshold value while keep applying the collector voltage V.sub.CE of a predetermined value, an n-channel would not be created and no collector current I.sub.c would be initiated. That is, the IGBT is cut off (i.e., turns off). When the collector voltage V.sub.CE is increased under OFF-state of the device by means of a reduction in the gate voltage V.sub.GE to zero or other suitable method, the collector current I.sub.c would not be started until the collector voltage V.sub.CE reaches a certain value. However, once the collector voltage V.sub.CE has grown beyond the certain value, the collector current I.sub.c will start flowing and become increasingly large. The collector voltage V.sub.CE at this stage is referred to as "breakdown voltage." The collector voltage V.sub.CE which can be applied to the IGBT is less than the breakdown voltage.
When the collector voltage V.sub.CE as large as about the breakdown voltage is applied to the IGBT, a depiction layer grows from the p-type base region 4 to as far as the buffer layer 2. If the depiction layer reaches the p-type semiconductor layer 1, the IGBT turns conductive from the p-type semiconductor layer 1 to the p-type base region 4 (known as "punch through"). The buffer layer 2, preventing growth of the depletion layer into the p-type semiconductor layer 1, obviates punch through.
&lt;Problems of Conventional Device&gt;
As can be readily understood from the device structure of the IGBT shown in FIG. 20, the IGBT includes a parasitic thyristor which is formed by the n-type emitter region 5, the n-type semiconductor layer 11 and the p-type semiconductor layer 1. The parasitic thyristor turns on if the collector current I.sub.c exceeds a certain value (i.e., latch up current) (Ts is known as "latching up of the IGBT"). Once the parasitic thyristor has turned on, no matter how the gate voltage V.sub.GE is controlled, it is impossible to control the collector current I.sub.c. The collector current I.sub.c then keeps flowing, eventually destroying the IGBT.
If the buffer layer 2 is formed having a thickness which would allow injection of holes from the p-type semiconductor layer 1 in a great number in order to reduce the ON-resistance, the value of the saturation collector current I.sub.c (sat) which is developed in response to application of a certain gate voltage V.sub.GE would increase. If the saturation collector current I.sub.c (sat) is large, the collector current I.sub.c tends to exceed the latch up current during the operations of the IGBT. The result of this is an increased possibility of destruction of the IGBT due to latch up.
Besides, constructed as a switching clement, in actual use, the IGBT occasionally turns conductive while a load is short circuited; that is, short circuiting is caused. When the IGBT short circuits, a current flowing in the IGBT is determined by the IGBT alone since there is no load any more which controls the collector current I.sub.c. FIG. 22 is a graph showing the waveform of the collector current I.sub.c with a change in time after the short circuiting. Immediately after the short circuiting, the collector current I.sub.c exhibits an abrupt increase, amounting to a maximum value which is about 5 to 20 times as large as the normal rated current value (50 to 150 A/cm.sup.2). It is when the collector current I.sub.c is at this maximum level that the IGBT is most likely to be destroyed due to latch up.
After the collector current I.sub.c reached the maximum level, even if latch up has not occurred, a continued unusually large collector current I.sub.c far beyond a normal level under normal environment is still observed. Due to this, the IGBT will be destroyed after a certain time Tv. The time Tv, during which the IGBT remains undestroyed though short circuiting, must be longer than 10 to 20 .mu.sec for practical reasons. In the art, it is a general knowledge that the lower the collector current I.sub.c is during short circuiting of the device, the longer the time Tv is. The collector current I.sub.c during short circuiting is defined at a value of the saturation collector current I.sub.c (sat).
If injection of an increased number of holes from the p-type semiconductor layer 1 is allowed by adjusting the buffer layer 2 to lower the ON-resistance as mentioned above, the value of the saturation collector current I.sub.c (sat) in response to application of a certain gate voltage V.sub.GE would increase. If the saturation collector current I.sub.c (sat) is large, the collector current I.sub.c under short circuiting becomes large, and therefore, the time Tv becomes short.
As heretofore described, the conventional IGBT has a drawback that a low ON-resistance easily causes destruction of the IGBT due to latch up and subsequent short circuiting (short-circuit destruction).